(1) Field of the Invention
The present invention relates to methods used for fabrication of high density, semiconductor memory cells, and more specifically to a process used to create a crown shaped capacitor structure, for a DRAM device, with increased capacitance resulting from the increased surface area of the crown shaped capacitor structure.
(2) Description of the Prior Art
The objectives of the semiconductor industry are to continually improve device performance, while still attempting to decrease the manufacturing cost of specific semiconductor chips. These objectives have been in part realized by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, and thus limiting the amount of area the overlying STC structure can occupy, without interfering with neighboring cells.
Solutions to the shrinking design area, assigned to STC structures, have been addressed via novel semiconductor fabrication processes which result in an increase in surface area for only the lower, or storage node electrode, of the STC structure, while maintaining the area original design area of the STC structure. One method for achieving this objective, described by Fazan, et al, in U.S. Pat. No. 5,278,091, is the creation of a lower polysilicon shape, or electrode, comprised of a hemispherical grained, (HSG) silicon layer, on the surface of the lower electrode. The rough surface of the HSG layer, results in an increase in lower electrode surface area, and thus an increase in STC capacitance. However the roughness of the HSG layer is strongly influenced by deposition conditions, making reproducibility of HSG roughness, and subsequent capacitance, difficult to achieve.
This invention will describe a process for fabricating a crown shaped, STC structure, obtained by forming the crown shape for the lower electrode, or storage node shape. The crown shaped, storage node structure, allows the increase in surface area, or capacitance, to be realized without the use of, the difficult to control, HSG deposition procedure. The crown shaped, storage node structure, described in this invention, is created using only two photolithographic masking procedures, and features novel processing sequences, such as timed, polysilicon, dry etching procedures, needed to fabricate the crown shaped, storage node structure, used for the crown shaped, STC structure.